15 search results - page 2 / 3 » Interblock memory for turbo coding |
ASAP
2008
IEEE
13 years 6 months ago
2008
IEEE
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
ISLPED
1998
ACM
13 years 9 months ago
1998
ACM
CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of t...
RSP
2008
IEEE
13 years 11 months ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
ICASSP
2011
IEEE
12 years 8 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards. Although several low-power techniques have been proposed,...