13 search results - page 1 / 3 » Interconnect parasitic extraction in the digital IC design m... |
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Abstract-- Due to photo-lithography effects and manufacture process variations, the actual features fabricated on the wafer are different from the designed ones. This difference ca...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
The long term impact of MEMS technology will be in its ability to integrate novel sensing and actuation functionality on traditional computing and communication devices enabling t...