A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects

Abstract-- Due to photo-lithography effects and manufacture process variations, the actual features fabricated on the wafer are different from the designed ones. This difference caused significant inaccuracy in interconnect parasitic, which is critical for timing verification. Existing layout parasitic extraction (LPE) tools ignore these effects, and result in inaccuracy. This paper presents a new methodology and fast algorithms for interconnect parasitic extraction considering photo-lithography effects and process variations. Compared with the traditional approach, the proposed methods are much more accurate. The new methodology can be embedded into the existing design flow with minimum changes, and use existing LPE tools.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Ying Zhou, Zhuo Li, Yuxin Tian, Weiping Shi, Frank Liu
• Keywords: ASPDAC 2007, Hardware, Parasitic Extraction, Photo-lithography Effects, Process Variations