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» Interconnect scaling implications for CAD
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ICCAD
1999
IEEE
78views Hardware» more  ICCAD 1999»
13 years 9 months ago
Interconnect scaling implications for CAD
Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz
DAC
2007
ACM
13 years 8 months ago
CAD Implications of New Interconnect Technologies
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a repl...
Louis Scheffer
GI
2009
Springer
13 years 9 months ago
Challenges of Electronic CAD in the Nano Scale Era
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets)...
Christian Hochberger, Andreas Koch
IPPS
2005
IEEE
13 years 10 months ago
Performance Implications of Periodic Checkpointing on Large-Scale Cluster Systems
Large-scale systems like BlueGene/L are susceptible to a number of software and hardware failures that can affect system performance. Periodic application checkpointing is a commo...
Adam J. Oliner, Ramendra K. Sahoo, José E. ...
TVLSI
2002
144views more  TVLSI 2002»
13 years 4 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail