21 search results - page 2 / 5 » Interconnect scaling implications for CAD |
DAC
2000
ACM
14 years 6 months ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
TCAD
2002
13 years 5 months ago
2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
IPPS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this work we examine the implications of building a single logical link out of multiple physical links. We use MultiEdge [12] to examine the throughput-CPU utilization tradeoff...