24 search results - page 2 / 5 » Interface timing verification with delay correlation using c... |
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
TCAD
2008
13 years 5 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
ICLP
1995
Springer
13 years 8 months ago
1995
Springer
The semantics of constraint logic programming languages with coroutining facilities (\freeze," suspension, residuation, etc.) cannot be fully declarative; thus, an operationa...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
CODES
2008
IEEE
13 years 7 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...