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» Intrabody Buses for Data and Power
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DAC
2003
ACM
14 years 6 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
13 years 11 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
HOTI
2008
IEEE
13 years 11 months ago
A High-Speed Optical Multi-Drop Bus for Computer Interconnections
Buses have historically provided a flexible communications structure in computer systems. However, signal integrity constraints of high-speed electronics have made multi-drop elec...
Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, ...
CODES
2005
IEEE
13 years 10 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...