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» Iterative remapping for logic circuits
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DAC
2005
ACM
14 years 6 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
13 years 9 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
FPGA
1995
ACM
110views FPGA» more  FPGA 1995»
13 years 8 months ago
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays
This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. Th...
Tong Liu, Wei-Kang Huang, Fabrizio Lombardi
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
13 years 11 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
TVLSI
2010
12 years 12 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...