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» JVM Susceptibility to Memory Errors
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IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
13 years 11 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
ISPASS
2005
IEEE
13 years 10 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
DSN
2002
IEEE
13 years 10 months ago
On the Placement of Software Mechanisms for Detection of Data Errors
An important aspect in the development of dependable software is to decide where to locate mechanisms for efficient error detection and recovery. We present a comparison between ...
Martin Hiller, Arshad Jhumka, Neeraj Suri
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 9 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
13 years 11 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand