9 search results - page 2 / 2 » LOT: Logic Optimization with Testability. New transformation... |
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
ETS
2010
IEEE
13 years 5 months ago
2010
IEEE
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...