248 search results - page 2 / 50 » Layered Switching for Networks on Chip |
ICPP
2007
IEEE
13 years 11 months ago
2007
IEEE
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
GLOBECOM
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
TCAD
2010
12 years 11 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...