19 search results - page 2 / 4 » Layout Decomposition Approaches for Double Patterning Lithog... |
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
In Double Patterning Lithography (DPL), conflict and stitch minimization are two main challenges. Post-routing mask decomposition algorithms [1
DAC
2009
ACM
14 years 5 months ago
2009
ACM
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...