129 search results - page 26 / 26 » Layout synthesis for datapath designs |
DAC
2005
ACM
13 years 7 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
BROADNETS
2004
IEEE
13 years 9 months ago
2004
IEEE
In this paper, we present a novel fully distributed version of a Mobile Backbone Network Topology Synthesis Algorithm (MBN-TSA) for constructing and maintaining a dynamic backbone...
DATE
2009
IEEE
13 years 12 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...