3 search results - page 1 / 1 » Layout-Aware Scan Chain Synthesis for Improved Path Delay Fa... |
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...