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» Layout-Oriented Synthesis of High Performance Analog Circuit...
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VTS
2003
IEEE
95views Hardware» more  VTS 2003»
13 years 11 months ago
Built-In Reseeding for Serial Bist
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost...
Ahmad A. Al-Yamani, Edward J. McCluskey
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
13 years 11 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 1 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ICCAD
2005
IEEE
87views Hardware» more  ICCAD 2005»
14 years 3 months ago
Statistical technology mapping for parametric yield
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky
DAC
2008
ACM
14 years 7 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...