8 search results - page 1 / 2 » Leakage Optimized DECAP Design for FPGAs |
APCCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— On-chip decoupling capacitors (Decaps) are widely used to mitigate on-chip power supply noise. At and below 100nm on-chip decaps face leakage and area overhead problems associa...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- This paper proposes a fast and practical decoupling capacitor (decap) budgeting algorithm to optimize the power ground (P/G) network design. The new method adopts a modified rand...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate lea...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
－ In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource...