8 search results - page 2 / 2 » Leakage Optimized DECAP Design for FPGAs |
ASPDAC
2009
ACM
13 years 10 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
-- Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects on ...