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ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 1 days ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
13 years 11 months ago
Thermal-induced leakage power optimization by redundant resource allocation
Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage wou...
Min Ni, Seda Ogrenci Memik
IJCAI
2007
13 years 6 months ago
Modeling When Connections Are the Problem
Most AI diagnostic reasoning approaches model components and but not their interconnections, and when they do model interconnections, they model the possibility that a connection ...
Johan de Kleer
CASES
2006
ACM
13 years 11 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
TVLSI
2008
99views more  TVLSI 2008»
13 years 5 months ago
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
Sheng-Chih Lin, Kaustav Banerjee