4 search results - page 1 / 1 » Leveraging application-level requirements in the design of a... |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems...
HOTI
2008
IEEE
13 years 11 months ago
2008
IEEE
The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-onchip...
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...