233 search results - page 2 / 47 » Logic design for low-voltage low-power CMOS circuits |
ASPDAC
2006
ACM
14 years 14 hour ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
ISLPED
1998
ACM
13 years 10 months ago
1998
ACM
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
- This paper describes the design of a low power
ISQED
2003
IEEE
13 years 11 months ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
CCECE
2006
IEEE
14 years 3 days ago
2006
IEEE
—This work presents a methodology for designing CMOS low-voltage low-power low-noise amplifiers (LNAs) based on the inductively degenerated common-source topology. To demonstrate...