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DATE
2004
IEEE
154views Hardware» more  DATE 2004»
13 years 9 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 7 hour ago
Priority based forced requeue to reduce worst-case latencies for bursty traffic
- In this paper we introduce Priority Based Forced Requeue to decrease worst-case latencies in NoCs offering best effort services. Forced Requeue is to prematurely lift out low pri...
Mikael Millberg, Axel Jantsch
HPCA
2009
IEEE
14 years 5 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...