35 search results - page 7 / 7 » Loop Scheduling and Partitions for Hiding Memory Latencies |
IWMM
2009
Springer
13 years 11 months ago
2009
Springer
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
RTAS
2005
IEEE
13 years 10 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
CASES
2006
ACM
13 years 8 months ago
2006
ACM
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
ASPLOS
2008
ACM
13 years 6 months ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
IEEEPACT
2005
IEEE
13 years 10 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...