47 search results - page 2 / 10 » Low voltage analog circuits using standard CMOS technology |
IJON
2007
13 years 5 months ago
2007
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed ...