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» Low-Power Properties of the Logarithmic Number System
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ARITH
2001
IEEE
13 years 8 months ago
Low-Power Properties of the Logarithmic Number System
Vassilis Paliouras, Thanos Stouraitis
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
13 years 10 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
13 years 10 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
DSD
2004
IEEE
106views Hardware» more  DSD 2004»
13 years 8 months ago
Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems
In this paper we present an analysis of the minimal hardware precision required to implement Support Vector Machine (SVM) classification within a Logarithmic Number System archite...
Faisal M. Khan, Mark G. Arnold, William M. Potteng...
ISCAS
2005
IEEE
142views Hardware» more  ISCAS 2005»
13 years 10 months ago
Hardware-based support vector machine classification in logarithmic number systems
—Support Vector Machines are emerging as a powerful machine-learning tool. Logarithmic Number Systems (LNS) utilize the property of logarithmic compression for numerical operatio...
Faisal M. Khan, Mark G. Arnold, William M. Potteng...