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» Low-power circuit advantages of the scaled accumulation FET
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ISCAS
2002
IEEE
96views Hardware» more  ISCAS 2002»
13 years 10 months ago
Low-power circuit advantages of the scaled accumulation FET
R. Murali, Lihui Wang, Blanca Austin, James D. Mei...
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
13 years 11 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
13 years 10 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 5 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija