16 search results - page 2 / 4 » Low-power high-level synthesis for FPGA architectures |
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
ERSA
2008
13 years 6 months ago
2008
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
DSD
2010
IEEE
13 years 3 months ago
2010
IEEE
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...