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» Making Pointer-Based Data Structures Cache Conscious
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LCTRTS
2007
Springer
13 years 11 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
EUROSYS
2011
ACM
12 years 8 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 8 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
MOBIDE
2005
ACM
13 years 10 months ago
Towards universal mobile caching
In the context of mobile data access, data caching is fundamental for both performance and functionality. For this reason there have been many studies into developing energy-effi...
Ganesh Santhanakrishnan, Ahmed Amer, Panos K. Chry...
CF
2006
ACM
13 years 6 months ago
Intermediately executed code is the key to find refactorings that improve temporal data locality
The growing speed gap between memory and processor makes an efficient use of the cache ever more important to reach high performance. One of the most important ways to improve cac...
Kristof Beyls, Erik H. D'Hollander