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» Mapping Applications to a Coarse Grain Reconfigurable System
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ERSA
2004
134views Hardware» more  ERSA 2004»
13 years 6 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner
ASAP
2005
IEEE
133views Hardware» more  ASAP 2005»
13 years 10 months ago
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware
In this paper, we propose a hardware/software partitioning method for improving applications’ performance in embedded systems. Critical software parts are accelerated on hardwar...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
13 years 10 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
IPPS
2007
IEEE
13 years 11 months ago
Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path
This paper presents the performance improvements and the energy reductions by coupling a highperformance coarse-grained reconfigurable data-path with a microprocessor in a generic...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
VLSISP
2008
123views more  VLSISP 2008»
13 years 4 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...