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» Massively parallel processing on a chip
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ALIFE
2002
13 years 5 months ago
Bioinspired Engineering of Exploration Systems for NASA and DoD
A new approach called bioinspired engineering of exploration systems (BEES) and its value for solving pressing NASA and DoD needs are described. Insects (for example honeybees and ...
Sarita Thakoor, Javaan S. Chahl, Mandyam V. Sriniv...
JPDC
2000
141views more  JPDC 2000»
13 years 5 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
13 years 3 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...
JSA
2010
173views more  JSA 2010»
13 years 2 days ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
HPCA
2009
IEEE
14 years 5 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...