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» Matrix Multiplication on Two Interconnected Processors
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DAC
2005
ACM
14 years 6 months ago
Flexible ASIC: shared masking for multiple media processors
ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micro...
Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potk...
SIES
2008
IEEE
13 years 11 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
IPPS
2008
IEEE
13 years 11 months ago
On the representation and multiplication of hypersparse matrices
Multicore processors are marking the beginning of a new era of computing where massive parallelism is available and necessary. Slightly slower but easy to parallelize kernels are ...
Aydin Buluç, John R. Gilbert
TVLSI
2010
13 years 12 hour ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
12 years 8 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross