Sciweavers

10 search results - page 2 / 2
» Matrix-Based Test Vector Decompression Using an Embedded Pro...
Sort
View
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
13 years 10 months ago
A Technique for High Ratio LZW Compression
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
Michael J. Knieser, Francis G. Wolff, Christos A. ...
DFT
2003
IEEE
100views VLSI» more  DFT 2003»
13 years 10 months ago
Scan-Based BIST Diagnosis Using an Embedded Processor
For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a sca...
Kedarnath J. Balakrishnan, Nur A. Touba
IJCNN
2008
IEEE
13 years 11 months ago
Using Variable Neighborhood Search to improve the Support Vector Machine performance in embedded automotive applications
— In this work we show that a metaheuristic, the Variable Neighborhood Search (VNS), can be effectively used in order to improve the performance of the hardware–friendly versio...
Enrique Alba, Davide Anguita, Alessandro Ghio, San...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
13 years 10 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
IH
2004
Springer
13 years 10 months ago
Feature-Based Steganalysis for JPEG Images and Its Implications for Future Design of Steganographic Schemes
In this paper, we introduce a new feature-based steganalytic method for JPEG images and use it as a benchmark for comparing JPEG steganographic algorithms and evaluating their embe...
Jessica J. Fridrich