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LCTRTS
2010
Springer
13 years 2 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
ICCAD
2003
IEEE
221views Hardware» more  ICCAD 2003»
14 years 1 months ago
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
Le Yan, Jiong Luo, Niraj K. Jha
WWW
2007
ACM
14 years 5 months ago
A scalable application placement controller for enterprise data centers
Given a set of machines and a set of Web applications with dynamically changing demands, an online application placement controller decides how many instances to run for each appl...
Chunqiang Tang, Malgorzata Steinder, Mike Spreitze...
DAC
2005
ACM
14 years 5 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 8 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang