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DATE
2002
IEEE
74views Hardware» more  DATE 2002»
13 years 9 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 1 months ago
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
Tianpei Zhang, Sachin S. Sapatnekar
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
13 years 9 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
SPAA
1999
ACM
13 years 9 months ago
Time-Constrained Scheduling of Weighted Packets on Trees and Meshes
The time-constrained packet routing problem is to schedule a set of packets to be transmitted through a multinode network, where every packet has a source and a destination (as in ...
Micah Adler, Sanjeev Khanna, Rajmohan Rajaraman, A...