3 search results - page 1 / 1 » Maze routing with buffer insertion and wiresizing |
DAC
2000
ACM
13 years 9 months ago
2000
ACM
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
ISQED
2002
IEEE
13 years 10 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...