12 search results - page 2 / 3 » Memory centric thread synchronization on platform FPGAs |
ICPP
2009
IEEE
14 years 27 days ago
2009
IEEE
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
ICMCS
2006
IEEE
14 years 8 days ago
2006
IEEE
In the near future, the majority of personal computers are expected to have several processing units. This is referred to as Core Multiprocessing (CMP). Furthermore, each of the c...
CF
2006
ACM
13 years 10 months ago
2006
ACM
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
EMSOFT
2010
Springer
13 years 4 months ago
2010
Springer
Nucleos is a new runtime system for ultra-lightweight embedded systems. Central to Nucleos is a dispatcher based on the concept of e threaded code, which enables layers of abstrac...
CODES
2009
IEEE
13 years 10 months ago
2009
IEEE
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...