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» Memory-aware NoC Exploration and Design
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DATE
2009
IEEE
178views Hardware» more  DATE 2009»
13 years 11 months ago
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Sam...
PPL
2008
185views more  PPL 2008»
13 years 4 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
DSD
2006
IEEE
99views Hardware» more  DSD 2006»
13 years 8 months ago
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis m...
Rikard Thid, Ingo Sander, Axel Jantsch
ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
13 years 5 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu