10 search results - page 1 / 2 » Microarchitectural Support for Speculative Register Renaming |
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
As a step torward a viable, single-issue out-of-order soft core, this work presents Copy-Free Checkpointing (CFC), an FPGA-friendly register renaming design. CFC supports speculat...
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
TPDS
2008
13 years 4 months ago
2008
This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads....