41 search results - page 2 / 9 » Microarchitectural Wire Management for Performance and Power... |
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
VLSID
2008
IEEE
14 years 5 months ago
2008
IEEE
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...