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» Microarchitecture in the system-level integration era
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DATE
2007
IEEE
109views Hardware» more  DATE 2007»
13 years 11 months ago
Microprocessors in the era of terascale integration
Moore’s Law will soon deliver tera-scale level transistor integration capacity. Power, variability, reliability, aging, and testing will pose as barriers and challenges to harne...
Shekhar Borkar, Norman P. Jouppi, Per Stenströ...
AHS
2007
IEEE
251views Hardware» more  AHS 2007»
13 years 8 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
HPCA
2009
IEEE
14 years 5 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
ICCAD
2009
IEEE
171views Hardware» more  ICCAD 2009»
13 years 2 months ago
A hybrid local-global approach for multi-core thermal management
Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have ne...
Ramkumar Jayaseelan, Tulika Mitra