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SBACPAD
2004
IEEE
86views Hardware» more  SBACPAD 2004»
13 years 6 months ago
Multi-Profile Instruction Based Compression
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
CODES
2005
IEEE
13 years 6 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
SBACPAD
2007
IEEE
143views Hardware» more  SBACPAD 2007»
13 years 11 months ago
A Code Compression Method to Cope with Security Hardware Overheads
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 11 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
DAC
2009
ACM
14 years 5 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong