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» Minimizing the Impact of Scan Compression
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VTS
2003
IEEE
95views Hardware» more  VTS 2003»
13 years 11 months ago
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
DCC
2010
IEEE
13 years 9 months ago
On the Adaptive Coefficient Scanning of JPEG XR/HD Photo
We explore several local and global strategies for adaptive scan ordering of transform coefficients in JPEG XR/HD Photo. This codec applies a global adaptive scan-order heuristic ...
Vanessa Testoni, Max H. M. Costa, Darko Kirovski, ...
DFT
2005
IEEE
132views VLSI» more  DFT 2005»
13 years 8 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
CVPR
2008
IEEE
14 years 8 months ago
An efficient algorithm for compressed MR imaging using total variation and wavelets
Compressed sensing, an emerging multidisciplinary field involving mathematics, probability, optimization, and signal processing, focuses on reconstructing an unknown signal from a...
Shiqian Ma, Wotao Yin, Yin Zhang, Amit Chakraborty
ITC
2003
IEEE
132views Hardware» more  ITC 2003»
13 years 11 months ago
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muh...