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» Multi-operand Floating-Point Addition
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TVLSI
2008
121views more  TVLSI 2008»
13 years 6 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
ERSA
2006
129views Hardware» more  ERSA 2006»
13 years 7 months ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao
SIAMSC
2008
168views more  SIAMSC 2008»
13 years 6 months ago
Accurate Floating-Point Summation Part II: Sign, K-Fold Faithful and Rounding to Nearest
In this Part II of this paper we first refine the analysis of error-free vector transformations presented in Part I. Based on that we present an algorithm for calculating the round...
Siegfried M. Rump, Takeshi Ogita, Shin'ichi Oishi
ASAP
2002
IEEE
170views Hardware» more  ASAP 2002»
13 years 11 months ago
Reviewing 4-to-2 Adders for Multi-Operand Addition
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
Peter Kornerup
ARITH
2005
IEEE
13 years 11 months ago
High-Radix Implementation of IEEE Floating-Point Addition
We are proposing a micro-architecture for highperformance IEEE floating-point addition that is based on a (non-redundant)high-radix representation of the floatingpoint operands....
Peter-Michael Seidel