Sciweavers

13 search results - page 2 / 3
» Multiple Design Error Diagnosis and Correction in Digital VL...
Sort
View
DAC
2005
ACM
13 years 7 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
13 years 10 months ago
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
Vishal Suthar, Shantanu Dutt
DAC
2010
ACM
13 years 8 months ago
Scalable specification mining for verification and diagnosis
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
Wenchao Li, Alessandro Forin, Sanjit A. Seshia
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 5 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
ISQED
2005
IEEE
108views Hardware» more  ISQED 2005»
13 years 10 months ago
Error Analysis for the Support of Robust Voltage Scaling
Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the...
David Roberts, Todd M. Austin, David Blaauw, Trevo...