234 search results - page 4 / 47 » Multiple Faults: Modeling, Simulation and Test |
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
VTS
2000
IEEE
13 years 10 months ago
2000
IEEE
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
VTS
2000
IEEE
13 years 10 months ago
2000
IEEE
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
VTS
2007
IEEE
14 years 1 days ago
2007
IEEE
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...