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» Nanometer Device Scaling in Subthreshold Circuits
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DAC
2007
ACM
14 years 5 months ago
Nanometer Device Scaling in Subthreshold Circuits
Scott Hanson, Mingoo Seok, Dennis Sylvester, David...
DATE
2005
IEEE
158views Hardware» more  DATE 2005»
13 years 10 months ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun ...
ISLPED
2009
ACM
127views Hardware» more  ISLPED 2009»
13 years 11 months ago
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
David Bol, Dina Kamel, Denis Flandre, Jean-Didier ...
DT
2006
109views more  DT 2006»
13 years 4 months ago
Test Consideration for Nanometer-Scale CMOS Circuits
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng