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» Network coding for routability improvement in VLSI
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ICCAD
2006
IEEE
122views Hardware» more  ICCAD 2006»
14 years 1 months ago
Network coding for routability improvement in VLSI
With the standard approach for establishing multicast connections over a network, network nodes are utilized to forward and duplicate the packets received over the incoming links....
Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulat...
SLIP
2005
ACM
13 years 10 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
ISVLSI
2006
IEEE
104views VLSI» more  ISVLSI 2006»
13 years 10 months ago
Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning
We describe analog and mixed-signal primitives for implementing adaptive signal-processing algorithms in VLSI based on anti-Hebbian learning. Both on-chip calibration techniques a...
Miguel Figueroa, Esteban Matamala, Gonzalo Carvaja...
VLSID
2006
IEEE
136views VLSI» more  VLSID 2006»
14 years 5 months ago
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal
Serial links in network on chip provide advantages in terms of reduced wiring area, reduced switch complexity and power. However, serial links offer lower bandwidth in comparison ...
Simon Ogg, Bashir M. Al-Hashimi
DFT
2009
IEEE
154views VLSI» more  DFT 2009»
13 years 11 months ago
Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
Qiaoyan Yu, Paul Ampadu