31 search results - page 2 / 7 » New Chips Move Networking onto Silicon |
IJES
2008
13 years 5 months ago
2008
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract—We describe a neuromorphic chip with a twolayer excitatory-inhibitory recurrent network of spiking neurons that exhibits localized clusters of neural activity. Unlike ot...
CICC
2011
12 years 5 months ago
2011
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
SIPS
2008
IEEE
13 years 12 months ago
2008
IEEE
Intellectual Properties (IPs) mapping algorithms for On-Chip-Networks (OCNs) allocate a set of IPs onto given network topologies. The existing mapping algorithms limit a single IP...
VLSID
2010
IEEE
13 years 9 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...