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» New models and algorithms for programmable networks
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FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
13 years 11 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
INFOCOM
2002
IEEE
13 years 10 months ago
Scheduling Processing Resources in Programmable Routers
—To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors are typi...
Prashanth Pappu, Tilman Wolf
ISCAS
2011
IEEE
278views Hardware» more  ISCAS 2011»
12 years 9 months ago
A programmable axonal propagation delay circuit for time-delay spiking neural networks
— we present an implementation of a programmable axonal propagation delay circuit which uses one first-order logdomain low-pass filter. Delays may be programmed in the 550ms rang...
Runchun Wang, Craig T. Jin, Alistair McEwan, Andr&...
INFOCOM
2006
IEEE
13 years 11 months ago
Intelligent Distribution of Intrusion Prevention Services on Programmable Routers
— The recent surge of new viruses and host attacks in the Internet and the tremendous propagation speed of selfdistributing attacks has made network security a pressing issue. To...
Andreas Hess, Hans-Florian Geerdes, Roland Wess&au...
DAC
2000
ACM
14 years 6 months ago
Depth optimal incremental mapping for field programmable gate arrays
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
Jason Cong, Hui Huang