54 search results - page 1 / 11 » NoC Power Estimation at the RTL Abstraction Level |
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
JSA
2010
12 years 11 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...