RTL Power Optimization with Gate-Level Accuracy

Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay information, the power optimization transformations applied at the RTL may cause unexpected results after synthesis, such as worsened delay or increased power dissipation. Our solution to this problem is to divide RTL power optimization into two steps, namely RTL exploration and gate-level commitment. During RTL exploration phase potential candidates for applying some specific RTL transformation are identified where high level information permits faster and more effective analysis. These candidates are simply “marked” on the netlist. Then during the gate-level commitment phase when accurate power and delay information is available, the final decision of whether accepting or rejecting the candidate is made to achieve the best power and delay trade-offs.

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Qi Wang, Sumit Roy
• Keywords: Hardware, ICCAD 2003, RTL Exploration Phase, RTL Power Optimization, Traditional RTL Power